S n
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Date
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Hr
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Topics to be Covered
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UNIT-I
MINIMIZATION TECHNIQUES AND LOGIC GATES
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1
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Introduction to Digital Electronics, Boolean postulates
and laws, De-Morgan’s Theorem.
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2
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Minimization of expressions using Boolean laws.
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3
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Minterm, Maxterm, Sum of Products (SOP), Product of Sums
(POS).
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4
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Minimization of expressions using Karnaugh map along with
don’t care conditions.
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5
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Minimization of expressions using Karnaugh map along with
don’t care conditions.
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6
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Quine-McCluskey method of minimization.
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7
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Truth table, symbol and expressions of AND, OR, NOT, NAND, NOR, Ex–OR and Ex–NOR.
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8
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Implementation of logic function using Universal gates,
Multi level gate implementations.
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9
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Multi output gate implementations.
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10
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TTL Logic and their characteristics,
Tristate gates.
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11
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CMOS Logic and their
characteristics, Tristate gates.
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12
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Tutorial
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UNIT –II COMBINATIONAL CIRCUITS
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1
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Design of half
adder and full adder.
|
2
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Design of half
subtractor, full subtractor and parallel binary adder/subtractor.
|
3
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Disadvantages of parallel adder and carry look ahead adder.
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4
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Design of serial
adder/subtractor and BCD adder.
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5
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Binary multiplier
and binary divider.
|
6
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Tutorial
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7
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Design and
implementation of Multiplexer and Demultiplexer.
|
8
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Encoder and
decoder.Odd,
|
9
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Code converters. |
10
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Even Parity checker and generators.
|
11
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2-bit, 4-bit Magnitude comparator
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12
|
|
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Tutorial
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UNIT –III SEQUENTIAL
CIRCUITS
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1
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Latches, Characteristic table and equation of SR, JK, D, and T flip flop.
|
2
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Latches, Characteristic table and equation of SR, JK, D, and T flip flop.
|
3
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Realizations of
one flip flop using other flip flops, Master-Slave flip flop.
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4
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Asynchronous ripple counter, Up/Down counter.
|
5
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Synchronous Up/Down counters,
|
6
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Programmable counters.
|
7
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State minimization
and State assignment.
|
8
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Design of Modulo-n counter.
|
9
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Shift registers, SISO, SIPO, PISO, PIPO and Universal
shift register.
|
10
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Ring counter and
shift counter.
|
11
|
|
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Design of sequence generators.
|
12
|
|
|
Tutorial
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UNIT –IV MEMORY DEVICES
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1
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Classification of memories-ROM, PROM, EPROM, EEPROM.
|
2
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RAM organization, write and read operation, Memory cycle
and Timing wave forms.
|
3
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Memory decoding and memory expansion.
|
4
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Static RAM Cell, Bipolar RAM cell and MOSFET RAM cell.
|
5
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Static RAM Cell, Bipolar RAM cell and MOSFET RAM cell.
|
6
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Introduction to Programmable Logic Devices.
|
7
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Implementation of combinational
logic circuits using PLA.
|
8
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Implementation of combinational
logic circuits using PAL.
|
9
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Field Programmable Gate Arrays
(FPGA).
|
10
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|
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Tutorial
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UNIT-V SYNCHRONOUS
AND AYNCHRONOUS SEQUENTIAL CIRCUITS
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1
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Algorithmic State Machine.
|
2
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General Model – Classification
|
3
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Analysis of Synchronous Sequential Circuits
|
4
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Design of fundamental mode.
|
5
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Design of fundamental mode.
|
6
|
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Design of Pulse mode.
|
7
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Design of Pulse mode.
|
8
|
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Hazards and types of hazards.
|
9
|
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Design of Hazard free switching circuits.
|
10
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Design of Combinational and Sequential
circuits using VERILOG.
|
11
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|
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Design of Combinational and Sequential
circuits using VERILOG.
|
12
|
|
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Tutorial
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Wednesday, July 2, 2014
Digital Electronics overview chart
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