Wednesday, July 2, 2014

Digital Electronics overview chart


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Date
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Topics to be Covered
UNIT-I MINIMIZATION TECHNIQUES AND LOGIC GATES 
1


Introduction to Digital Electronics, Boolean postulates and laws, De-Morgan’s Theorem.
2


Minimization of expressions using Boolean laws.
3


Minterm, Maxterm, Sum of Products (SOP), Product of Sums (POS).
4


Minimization of expressions using Karnaugh map along with don’t care conditions.
5


Minimization of expressions using Karnaugh map along with don’t care conditions.
6


Quine-McCluskey method of minimization.
7

 
Truth table, symbol and expressions of AND, OR, NOT, NAND, NOR, Ex–OR and Ex–NOR.
8


Implementation of logic function using Universal gates, Multi level gate implementations.
9


Multi output gate implementations.
10


TTL Logic and their characteristics, Tristate gates.
11


CMOS Logic and their characteristics, Tristate gates.
12


Tutorial
UNIT –II COMBINATIONAL CIRCUITS
1


Design of half adder and full adder.
2


Design of half subtractor, full subtractor and parallel binary adder/subtractor.
3

 
Disadvantages of parallel adder and carry look ahead adder.
4


Design of serial adder/subtractor and BCD adder.
5


Binary multiplier and binary divider.
6


Tutorial
7


Design and implementation of Multiplexer and Demultiplexer.
8


Encoder and decoder.Odd,
9

 
Code converters.
10


Even Parity checker and generators.
11


2-bit, 4-bit Magnitude comparator
12


Tutorial
UNIT –III SEQUENTIAL CIRCUITS
1


Latches, Characteristic table and equation of SR, JK, D, and T flip flop.
2


Latches, Characteristic table and equation of SR, JK, D, and T flip flop.
3


Realizations of one flip flop using other flip flops, Master-Slave flip flop.
4


Asynchronous ripple counter, Up/Down counter.
5


Synchronous Up/Down counters,
6


Programmable counters.
7


State minimization and State assignment.
8


Design of Modulo-n counter.
9


Shift registers, SISO, SIPO, PISO, PIPO and Universal shift register.
10


Ring counter and shift counter.
11


Design of sequence generators.
12


Tutorial
UNIT –IV MEMORY DEVICES
1


Classification of memories-ROM, PROM, EPROM, EEPROM.
2


RAM organization, write and read operation, Memory cycle and Timing wave forms.
3


Memory decoding and memory expansion.
4


Static RAM Cell, Bipolar RAM cell and MOSFET RAM cell.
5


Static RAM Cell, Bipolar RAM cell and MOSFET RAM cell.
6


Introduction to Programmable Logic Devices.
7


Implementation of combinational logic circuits using PLA.
8


Implementation of combinational logic circuits using PAL.
9


Field Programmable Gate Arrays (FPGA).
10


Tutorial
UNIT-V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS
1


Algorithmic State Machine.
2


General Model – Classification
3


Analysis of Synchronous Sequential Circuits
4


Design of fundamental mode.
5


Design of fundamental mode.
6


Design of Pulse mode.
7


Design of Pulse mode.
8


Hazards and types of hazards.
9


Design of Hazard free switching circuits.
10


Design of Combinational and Sequential circuits using VERILOG.
11


Design of Combinational and Sequential circuits using VERILOG.
12


Tutorial


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